Single Event Gate Rupture (SEGR) Simulations in Vertical Planar Power MOSFETs
نویسندگان
چکیده
Introduction Power MOSFETs exposed to particle-rich, space-like or terrestrial, environment, can exhibit Single Event Gate Rupture (SEGR) and Single Event Burnout (SEB). The use of power devices as high power solid state switches for the electric and hybrid car manufacturers, has generated new non-military, and non-space interest power device failure modes. A SEGR event is one such failure mode and the simulation of such an event is the subject of this article.
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